Regviz

Espressif Systems /ESP32-S2 /PMS /CPU_PERIPHERAL_INTR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CPU_PERIPHERAL_INTR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S2/PMS/CPU_PERIPHERAL_INTR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CPU_PERI_BYTE_ERROR_CLR)CPU_PERI_BYTE_ERROR_CLR 0 (CPU_PERI_BYTE_ERROR_EN)CPU_PERI_BYTE_ERROR_EN 0 (CPU_PERI_BYTE_ERROR_INTR)CPU_PERI_BYTE_ERROR_INTR

Description

PeribBus1 permission control register.

Fields

CPU_PERI_BYTE_ERROR_CLR

The clear signal for CPU peripheral access interrupt.
CPU_PERI_BYTE_ERROR_EN

The enable signal for CPU peripheral access interrupt.
CPU_PERI_BYTE_ERROR_INTR

CPU peripheral access interrupt signal.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data